HD64F3039F18 Datasheet, PDF (658/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Appendix B Internal I/O Register Field
SSR—Serial Status Register
H'B4
SCI0
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Multiprocessor bit
0 Multiprocessor bit value in
receive data is 0
Multiprocessor bit transfer
0 Multiprocessor bit value in
transmit data is 0
Transmit end
1 Multiprocessor bit value in
receive data is 1
0 [Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
1 Multiprocessor bit value in
transmit data is 1
1 [Setting conditions]
Reset or transition to standby mode.
TE is cleared to 0 in SCR.
TDRE is 1 when last bit of serial character is transmitted.
Framing error
0 [Clearing conditions]
Reset or transition to standby mode.
Read FER when FER = 1, then write 0
in FER.
1 [Setting condition]
Framing error (stop bit is 0)
Parity error
0 [Clearing conditions]
Reset or transition to standby mode.
Read PER when PER = 1, then write 0 in
PER.
1 [Setting condition]
Parity error: (parity of receive data does not
match parity setting of O/E in SMR)
Receive data register full
0 [Clearing conditions]
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
1 [Setting condition]
Serial data is received normally and transferred
from RSR to RDR
Overrun error
0 [Clearing conditions]
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
ORER.
1 [Setting condition]
Overrun error (reception of next serial data
ends when RDRF = 1)
Transmit data register empty
0 [Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
1 [Setting conditions]
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
data to be written in TDR.
Note: * Only 0 can be written to clear the flag.
Rev.3.00 Mar. 26, 2007 Page 634 of 682
REJ09B0353-0300