HD64F3039F18 Datasheet, PDF (143/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

6.3 Operation
Section 6 Bus Controller
6.3.1 Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the
1-Mbyte mode and 2 Mbytes in the 16-Mbyte mode. Figure 6.2 shows a general view of the
memory map.
H'00000
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0 (128 kbytes)
Area 1 (128 kbytes)
Area 2 (128 kbytes)
Area 3 (128 kbytes)
Area 4 (128 kbytes)
Area 5 (128 kbytes)
Area 6 (128 kbytes)
Area 7 (128 kbytes)
H'000000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Area 0 (2 Mbytes)
Area 1 (2 Mbytes)
Area 2 (2 Mbytes)
Area 3 (2 Mbytes)
Area 4 (2 Mbytes)
Area 5 (2 Mbytes)
Area 6 (2 Mbytes)
Area 7 (2 Mbytes)
H'00000
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
On-chip ROM^*1
Area 0 (128 kbytes)
Area 1 (128 kbytes)
Area 2 (128 kbytes)
Area 3 (128 kbytes)
Area 4 (128 kbytes)
Area 5 (128 kbytes)
Area 6 (128 kbytes)
Area 7 (128 kbytes)
On-chip RAM^{*1 *2}
On-chip RAM^{*1 *2}
On-chip RAM^{*1 *2}
External address space^*3
External address space^*3
External address space^*3
H'FFFFF ^{On-chip I/O registers*1} H'FFFFFF ^{On-chip I/O registers*1} H'FFFFF ^{On-chip I/O registers*1}
a. 1-Mbyte modes with
on-chip ROM disabled
(mode 1)
b. 16-Mbyte modes with
on-chip ROM disabled
(mode 3)
c. 1-Mbyte mode with
on-chip ROM enabled
(mode 5)
Notes: There is no area division in modes 6 and 7.
1. The number of access states to on-chip ROM, on-chip RAM, and on-chip I/O registers is fixed.
2. This area follows area 7 specifications when the RAME bit in SYSCR is 0.
3. This area follows area 7 specifications.
Figure 6.2 Access Area Map (Mode 1, 3, and 5)
Rev.3.00 Mar. 26, 2007 Page 119 of 682
REJ09B0353-0300