HD64F3039F18 Datasheet, PDF (555/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 18 Electrical Characteristics
Condition A Condition B Condition C
Item
8 MHz
Symbol Min Max
10 MHz
Min Max
18 MHz
Test
Min Max Unit Conditions
Write data delay time
Write data setup time 1
t_WDD
— 75
— 75
— 55 ns Figure 18.7,
t_WDS1
60 —
40 —
10 —
Figure 18.8
Write data setup time 2
t_WDS2
5
—
–10 —
–10 —
Write data hold time
t_WDH
25 —
20 —
20 —
Read data access time 1
t * _ACC1
— 120 — 100 — 50
Read data access time 2
t * _ACC2
— 240 — 200 — 105
Read data access time 3
t * _ACC3
— 70
— 50
— 20
Read data access time 4
t * _ACC4
— 180 — 150 — 80
Precharge time
t_PCH*
85 —
60 —
40 —
Wait setup time
t_WTS
40 —
40 —
25 —
Figure 18.9
Wait hold time
t_WTH
10 —
10 —
5
—
Note: * For Condition A, the following times depend on the clock cycle time as shown below.
t_ACC1 = 1.5 × t_cyc –68
t_ACC2 = 2.5 × t_cyc –73
t
ACC3
=
1.0
×
t
cyc
–55
t_ACC4 = 2.0 × t_cyc –70
(ns)
(ns)
(ns)
(ns)
t_WSW1 = 1.0 × t_cyc –40
t_WSW2 = 1.5 × t_cyc –38
t
PCH
=
1.0
×
t
cyc
–40
(ns)
(ns)
(ns)
For Condition B, the following times depend on the clock cycle time as shown below.
t_ACC1 = 1.5 × t_cyc –50
t
ACC2
=
2.5
×
t
cyc
–50
t_ACC3 = 1.0 × t_cyc –50
t_ACC4 = 2.0 × t_cyc –50
(ns)
(ns)
(ns)
(ns)
t_WSW1 = 1.0 × t_cyc –40
t
WSW2
=
1.5
×
t
cyc
–40
t_PCH = 1.0 × t_cyc –40
(ns)
(ns)
(ns)
For Condition C, the following times depend on the clock cycle time as shown below.
t
ACC1
=
1.5
×
t
cyc
–34
t_ACC2 = 2.5 × t_cyc –34
t_ACC3 = 1.0 × t_cyc –36
t_ACC4 = 2.0 × t_cyc –31
(ns)
(ns)
(ns)
(ns)
t
WSW1
=
1.0
×
t
cyc
–24
t_WSW2 = 1.5 × t_cyc –22
t_PCH = 1.0 × t_cyc –21
(ns)
(ns)
(ns)
Rev.3.00 Mar. 26, 2007 Page 531 of 682
REJ09B0353-0300