HD64F3039F18 Datasheet, PDF (10/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Item
Page
5.3.3 Interrupt Vector 98
Table
Table 5.3 Interrupt
Sources, Vector
Addresses, and Priority
5.5.4 Usage Notes 109
Figure 5.9 IRQnF Flag
when Interrupt
Exception Handling is
not Executed
Revision (See Manual for Details)
Table amended
WOVI (interval timer)
Figure amended
1 read 0 written
6.4.2 Precautions on 131
Setting ASTCR and
ABWCR*
11.2.8 Bit Rate
349
Register (BRR)
Table 11.3 Examples 351
of Bit Rates and BRR
Settings in
Asynchronous Mode
11.3.4 Synchronous 376
Operation
Clock
1 read 0
written
(Inadvertent clearing)
Generation condition (2)
Description amended
Modes 5 and 7
ASTCR0 = 0
ABWCR = H'FC
Description added
The baud rate generator is controlled separately for the
individual channels, so different values may be set for each.
Table amended
φ (MHz)
12
Bit Rate
(bits/s) n N
Error
(%)
300
2 77 0.16
Description amended
An internal clock generated by the on-chip baud rate generator
or an external clock input from the SCK pin can be selected by
clearing or setting the CKE1 and CKE0 bits in SCR and the C/A
bit in SMR. See table 11.9.
Rev.3.00 Mar. 26, 2007 Page viii of xxii
REJ09B0353-0300