HD64F3039F18 Datasheet, PDF (131/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

5.5 Usage Notes
Section 5 Interrupt Controller
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the ITU's TIER.
φ
Internal
address bus
Internal
write signal
IMIEA
TIER write cycle by CPU
TIER address
IMIA exception handling
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
Rev.3.00 Mar. 26, 2007 Page 107 of 682
REJ09B0353-0300