HD64F3039F18 Datasheet, PDF (75/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 2 CPU
Exception
sources
Reset
Interrupt
Trap instruction
External interrupts
Internal interrupts (from on-chip supporting modules)
Figure 2.12 Classification of Exception Sources
End of
exception
handling
Program execution state
Exception
SLEEP
instruction
with SSBY = 0
Sleep mode
Exception-handling state
Interrupt
NMI, IRQ₀, IRQ ₁,
or IRQ ₂ interrupt
SLEEP instruction
with SSBY = 1
Software standby mode
RES = high
Reset state^*1
STBY = high, RES = low
Hardware standby mode^*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions
2.8.4 Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
Rev.3.00 Mar. 26, 2007 Page 51 of 682
REJ09B0353-0300