HD64F3039F18 Datasheet, PDF (296/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.5 Interrupts
The ITU has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
8.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match
IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general
register (GR). The compare match signal is generated in the last state in which the values match
(when TCNT is updated from the matching count to the next count). Therefore, when TCNT
matches a general register, the compare match signal is not generated until the next timer clock
input. Figure 8.57 shows the timing of the setting of IMFA and IMFB.
φ
TCNT input
clock
TCNT
N
N+1
GR
N
Compare
match signal
IMF
IMI
Figure 8.57 Timing of Setting of IMFA and IMFB by Compare Match
Rev.3.00 Mar. 26, 2007 Page 272 of 682
REJ09B0353-0300