HD64F3039F18 Datasheet, PDF (370/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 11 Serial Communication Interface
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial transmit data can be written in TDR.
Bit 7
TDRE
0
1
Description
TDR contains valid transmit data
[Clearing condition]
Software reads TDRE while it is set to 1, then writes 0
TDR does not contain valid transmit data
(Initial value)
[Setting conditions]
• The chip is reset or enters standby mode
• The TE bit in SCR is cleared to 0
• TDR contents are loaded into TSR, so new data can be written in TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF
Description
0
RDR does not contain new receive data
(Initial value)
[Clearing conditions]
• The chip is reset or enters standby mode
• Software reads RDRF while it is set to 1, then writes 0
• The DMAC reads data from RDR
1
RDR contains new receive data
[Setting condition]
When serial data is received normally and transferred from RSR to RDR
Note:
The RDR contents and RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error occurs and receive data is
lost.
Rev.3.00 Mar. 26, 2007 Page 346 of 682
REJ09B0353-0300