HD64F3039F18 Datasheet, PDF (378/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 11 Serial Communication Interface
The BRR setting is calculated as follows:
Asynchronous mode:
N=
φ
× 10⁶ – 1
64 × 2^2n–1 × B
Synchronous mode:
N=
φ
× 10⁶ – 1
8 × 2^2n–1 × B
B: Bit rate (bits/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: System clock frequency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
n
Clock Source
CKS1
0
φ
0
1
φ/4
0
2
φ/16
1
3
φ/64
1
SMR Settings
CKS0
0
1
0
1
The bit rate error in asynchronous mode is calculated as follows.
Error (%) = {
(N
+
1)
φ ×10⁶
× B × 64
×
2^2n–1
–
1}
×
100
Rev.3.00 Mar. 26, 2007 Page 354 of 682
REJ09B0353-0300