HD64F3039F18 Datasheet, PDF (493/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 15 ROM
Table 15.8 Hardware Protection
Function
Item
Description
Program Erase Verify*¹
FWE pin
protection
• When a low level is input to the FWE
No*²
No*³
No
pin, FLMCR and EBR are initialized,
and the program/erase-protected state
is entered.*⁴
Reset/standby • In a reset (including a WDT overflow
No
protection
reset) and in standby mode, FLMCR
and EBR are initialized, and the
program/erase-protected state is
entered.
No*³
No
• In a reset via the RES pin, the reset
state is not entered unless the RES pin
is held low until oscillation stabilizes
after powering on (The minimum
oscillation stabilization time is 20ms).
In the case of a reset during operation,
hold the RES pin low for at least 20
system clock cycles.*⁵
Error protection • When a microcomputer operation error No
(error generation (FLER=1)) was
detected while flash memory was being
No*³
Yes
programmed/erased, error protection is
enabled. At this time, the FLMCR and
EBR settings are held, but
programming/erasing is aborted at the
time the error was generated. Error
protection is released only by a reset
via the RES pin or a WDT reset, or in
the hardware standby mode.
Notes: 1. Two modes: program-verify and erase-verify.
2. The RAM area that overlapped flash memory is deleted.
3. All blocks become unerasable and specification by block is impossible.
4. For more information, see section 15.9, Notes on Flash Memory Programming/Erasing.
5. See sections 4.2.2, Reset Sequence and 15.9, Notes on Flash Memory
Programming/Erasing. This LSI requires a minimum reset time during operation of 20
system clocks.
Rev.3.00 Mar. 26, 2007 Page 469 of 682
REJ09B0353-0300