HD64F3039F18 Datasheet, PDF (66/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 2 CPU
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode
1
Register direct
2
Register indirect
3
Register indirect with displacement
4
Register indirect with post-increment
Register indirect with pre-decrement
5
Absolute address
6
Immediate
7
Program-counter relative
8
Memory indirect
Symbol
Rn
@ERn
@(d:16, ERn)/@d:24, ERn)
@Ern+
@–ERn
@aa:8/@aa:16/@aa:24
#xx:8/#xx:16/#xx:32
@(d:8, PC)/@(d:16, PC)
@@aa:8
1. Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2. Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand.
3. Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an
address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the
sum specify the address of a memory operand. A 16-bit displacement is sign-extended when
added.
Rev.3.00 Mar. 26, 2007 Page 42 of 682
REJ09B0353-0300