HD64F3039F18 Datasheet, PDF (220/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Block Diagram of Channel 2
Figure 8.3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1
output.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Clock selector
Comparator
Control logic
TIOCA₂
TIOCB₂
IMIA2
IMIB2
OVI2
Module data bus
Legend:
TCNT2:
Timer counter 2 (16 bits)
GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
TCR2:
Timer control register 2 (8 bits)
TIOR2:
TIER2:
TSR2:
Timer I/O control register 2 (8 bits)
Timer interrupt enable register 2 (8 bits)
Timer status register 2 (8 bits)
Figure 8.3 Block Diagram of Channel 2
Rev.3.00 Mar. 26, 2007 Page 196 of 682
REJ09B0353-0300