HD64F3039F18 Datasheet, PDF (535/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 17 Power-Down State
17.2.2 Module Standby Control Register (MSTCR)
MSTCR is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the ITU, SCI0, SCI1, and A/D converter
modules.
Bit
Initial value
Read/Write
7
PSTOP
0
R/W
6
5
4
3
2
— MSTOP5 MSTOP4 MSTOP3 —
1
0
0
0
0
—
R/W R/W R/W
—
1
0
— MSTOP0
0
0
—
R/W
Reserved bit
Reserved bit
φ clock stop
Enables or disables
output of the system clock
Module standby 5 to 3, and 0
These bits select modules
to be placed in standby
MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 7
PSTOP
0
1
Description
System clock output is enabled
System clock output is disabled
(Initial value)
Bit 6—Reserved: This bit cannot be modified and is always read as 1.
Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.
Bit 5
MSTOP5
0
1
Description
ITU operates normally
ITU is in standby state
(Initial value)
Rev.3.00 Mar. 26, 2007 Page 511 of 682
REJ09B0353-0300