HD64F3039F18 Datasheet, PDF (141/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 6 Bus Controller
6.2.4 Address Control Register (ADRCR)
ADRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A21.
Bit
7
6
5
4
3
2
1
0
A₂₃E
A₂₂E
A₂₁E
—
—
—
—
—
Modes 1 ^{Initial value}
1
1
1
1
1
1
1
0
and 5 to 7 _Read/Write
—
—
—
—
—
—
—
R/W
Initial value
1
1
1
1
1
1
1
0
Mode 3
Read/Write R/W
R/W
R/W
—
—
—
—
R/W
Address 23 to 21 enable
These bits enable PA₆ to
PA₄ to be used for A₂₃ to
A₂₁ address output
Reserved bits
ADRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Address 23 Enable (A₂₃E): Enables PA4 to be used as the A₂₃ address output pin. Writing
0 in this bit enables A₂₃ address output from PA4. In modes other than 3 this bit cannot be
modified and PA4 has its ordinary input/output functions
Bit 7
A₂₃E
0
1
Description
PA₄ is the A₂₃ address output pin
PA₄ is the PA₄/TP₄/TIOCA₁ input/output pin
(Initial value)
Bit 6—Address 22 Enable (A₂₂E): Enables PA₅ to be used as the A₂₂ address output pin. Writing 0
in this bit enables A₂₂ address output from PA₅. In modes other than 3 this bit cannot be modified
and PA₅ has its ordinary input/output functions.
Bit 6
AE
22
0
1
Description
PA is the A address output pin
5
22
PA is the PA /TP /TIOCB input/output pin
5
5
5
1
(Initial value)
Rev.3.00 Mar. 26, 2007 Page 117 of 682
REJ09B0353-0300