HD64F3039F18 Datasheet, PDF (340/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before
the next compare match B occurs.
Figure 9.10 shows the timing relationships.
Compare
match A
Compare
match B
NDR write
NDR write
NDR
DR
0 output 0/1 output
0 output
0/1 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
Write to NDR
in this interval
Do not write
to NDR in this
interval
Figure 9.10 Non-Overlapping Operation and NDR Write Timing
Rev.3.00 Mar. 26, 2007 Page 316 of 682
REJ09B0353-0300