HD64F3039F18 Datasheet, PDF (591/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Appendix A Instruction Set
Addressing Mode and
Instruction Length (bytes)
No. of
States^*1
Mnemonic
INC.L #1, ERd
INC.L #2, ERd
DAA Rd
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.L #1, ERd
SUBS.L #2, ERd
SUBS.L #4, ERd
DEC.B Rd
DEC.W #1, Rd
DEC.W #2, Rd
DEC.L #1, ERd
DEC.L #2, ERd
DAS.Rd
MULXU. B Rs, Rd
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS. W Rs, ERd
DIVXU. B Rs, Rd
Operation
L ERd32+1 → ERd32
L ERd32+2 → ERd32
B Rd8 decimal adjust
→ Rd8
B Rd8–Rs8 → Rd8
W Rd16–#xx:16 → Rd16
W Rd16–Rs16 → Rd16
L ERd32–#xx:32
→ ERd32
L ERd32–ERs32
→ ERd32
B Rd8–#xx:8–C → Rd8
B Rd8–Rs8–C → Rd8
L ERd32–1 → ERd32
L ERd32–2 → ERd32
L ERd32–4 → ERd32
B Rd8–1 → Rd8
W Rd16–1 → Rd16
W Rd16–2 → Rd16
L ERd32–1 → ERd32
L ERd32–2 → ERd32
B Rd8 decimal adjust
→ Rd8
B Rd8 × Rs8 → Rd16
(unsigned multiplication)
W Rd16 × Rs16 → ERd32
(unsigned multiplication)
B Rd8 × Rs8 → Rd16
(signed multiplication)
W Rd16 × Rs16 → ERd32
(signed multiplication)
B Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
2
2
2
2
4
2
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
2
Condition Code
I HNZVC
——
—
2
——
—
2
—*
*—
2
—
2
— (1)
4
— (1)
2
— (2)
6
— (2)
2
—
(3)
2
—
(3)
2
——————
2
——————
2
——————
2
——
—
2
——
—
2
——
—
2
——
—
2
——
—
2
—*
*—
2
——————
14
——————
22
——
——
16
——
——
24
— — (6) (7) — —
14
Rev.3.00 Mar. 26, 2007 Page 567 of 682
REJ09B0353-0300