HD64F3039F18 Datasheet, PDF (634/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Appendix B Internal I/O Register Field
TSR0—Timer Status Register 0
H'67
ITU0
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF IMFB IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
— R/(W)* R/(W)* R/(W)*
Input capture/compare match flag A
0 [Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA
1 [Setting conditions]
• TCNT = GRA when GRA functions as a compare
match register.
• TCNT value is transferred to GRA by an input capture
signal, when GRA functions as an input capture register.
Input capture/compare match flag B
0 [Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
1 [Setting conditions]
• TCNT = GRB when GRB functions as a compare
match register.
• TCNT value is transferred to GRB by an input capture
signal, when GRB functions as an input capture register.
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000
Note: * Only 0 can be written to clear the flag.
Rev.3.00 Mar. 26, 2007 Page 610 of 682
REJ09B0353-0300