HD64F3039F18 Datasheet, PDF (120/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 5 Interrupt Controller
5.3 Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ₅, IRQ₄, IRQ₁ and IRQ₀) and 25
internal interrupts.
5.3.1 External Interrupts
There are five external interrupts: NMI, and IRQ₅, IRQ₄, IRQ₁, and IRQ₀. Of these, NMI, IRQ0,
IRQ1, can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the
I and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
IRQ₅, IRQ₄, IRQ₁, IRQ₀ Interrupts: These interrupts are requested by input signals at pins IRQ₅,
IRQ₄, IRQ₁, IRQ₀. The IRQ₅, IRQ₄, IRQ₁, IRQ₀ interrupts have the following features.
• ISCR settings can select whether an interrupt is requested by the low level of the input at pins
IRQ₅, IRQ₄, IRQ₁, IRQ₀, or by the falling edge.
• IER settings can enable or disable the IRQ₅, IRQ₄, IRQ₁, IRQ₀ interrupts.
Interrupt priority levels can be assigned by four bits in IPRA (IPRA7, IPRA6, and IPRA4).
• The status of IRQ₅, IRQ₄, IRQ₁, IRQ₀ interrupt requests is indicated in ISR. The ISR flags can
be cleared to 0 by software.
Figure 5.2 shows a block diagram of interrupts IRQ₅, IRQ₄, IRQ₁, IRQ₀.
IRQnSC
IRQnE
IRQn input
Edge/level
sense circuit
IRQnF
S
Q
R
Clear signal
IRQn interrupt
request
Note: n = 5, 4, 1 and 0
Figure 5.2 Block Diagram of Interrupts IRQ₅, IRQ₄, IRQ₁, and IRQ₀
Rev.3.00 Mar. 26, 2007 Page 96 of 682
REJ09B0353-0300