 English |
|
|
|
|
|
|
|
| HD64F3039F18 Datasheet, PDF (239/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series | |||
| |||
| ◁ |
Section 8 16-Bit Integrated Timer Unit (ITU)
Bit 3âMaster Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB3.
Bit 3
EB3
0
1
Description
TIOCB3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3 operates as
a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
TIOCB3 is enabled for output according to TIOR3 and TFCR settings (Initial value)
Bit 2âMaster Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4.
Bit 2
EB4
0
1
Description
TIOCB output is disabled regardless of TIOR4 and TFCR settings (TIOCB operates as
4
4
a generic input/output pin).
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
TIOCB is enabled for output according to TIOR4 and TFCR settings (Initial value)
4
Bit 1âMaster Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4.
Bit 1
EA4
0
1
Description
TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4
operates as a generic input/output pin).
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
TIOCA4 is enabled for output according to TIOR4, TMDR, and TFCR settings
(Initial value)
Bit 0âMaster Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3.
Bit 0
EA3
0
1
Description
TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3
operates as a generic input/output pin).
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
TIOCA3 is enabled for output according to TIOR3, TMDR, and TFCR settings
(Initial value)
Rev.3.00 Mar. 26, 2007 Page 215 of 682
REJ09B0353-0300
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese