HD64F3039F18 Datasheet, PDF (491/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 15 ROM
Start
*1
Set SWE bit in FLMCR
Wait (x) µs
Erase counter n ← 1
Set EBR
Enable WDT
Set ESU bit in FLMCR
Wait (y) µs
Set E bit in FLMCR
Wait (z) ms
Clear E bit in FLMCR
Wait (α) µs
*2
*4
*5
*2
Start of erase
*2
End of erase
*2
Clear ESU bit in FLMCR
Wait (β) µs
*2
Disable WDT
Set EV bit in FLMCR
Wait (γ) µs
*2
Set block start address
to verify address
H'FF dummy write to verify address
Wait (ε) µs
*2
Read verify data
*3
Increment
verify address
No
No
Verify data = H'FFFF?
YES
Last address of block?
Yes
*2
Clear EV bit in FLMCR
Wait (η) µs
Clear SWE bit in FLMCR
End of erasing
n←n+1
Clear EV bit in FLMCR
Wait (η) µs
Re-erase
*2
*2
No
n > N?
Yes
Clear SWE bit in FLMCR
Erase failure
Notes: 1. Preprogramming (setting erase block data to all 0s) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, and N are shown in section 18.2.5, Flash Memory Characteristics.
3. Verify data is read in 16-bit (word) units. (Byte-unit reading is also possible.)
4. Set only one bit in EBR two or more bits must not be set simultaneously.
5. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Figure 15.12 Erase/Erase-Verify Flowchart (Single-Block Erasing)
Rev.3.00 Mar. 26, 2007 Page 467 of 682
REJ09B0353-0300