HD64F3039F18 Datasheet, PDF (466/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 15 ROM
15.2.3 Pin Configuration
The flash memory is controlled by means of the pins shown in table 15.2.
Table 15.2 Flash Memory Pins
Pin Name
Abbreviation I/O
Function
Reset
RES
Input Reset
Flash write enable FWE*
Input Flash program/erase protection by hardware
Mode 2
MD
Input Sets this LSI operating mode
2
Mode 1
MD
Input Sets this LSI operating mode
1
Mode 0
MD₀
Input Sets this LSI operating mode
Transmit data
TxD₁
Output Serial transmit data output
Receive data
RxD
1
Input Serial receive data input
Notes: The transmit data and receive data pins are used in boot mode.
* In the mask ROM versions, the FWE pin functions as the RESO pin.
15.2.4 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 15.3.
Table 15.3 Flash Memory Registers
Register Name
Abbreviation R/W
Initial Value
Flash memory control register FLMCR
R/W
H'00*²
Erase block register
EBR
R/W
H'00
RAM control register
RAMCR
R/W
H'F1
Flash memory status register FLMSR
R
H'7F
Notes: 1. Lower 16 bits of the address.
2. When a high level is input to the FWE pin, the initial value is H'80.
Address*¹
H'FF40
H'FF42
H'FF47
H'FF4D
The registers in table 15.3 are used in the flash memory versions only. Reading the corresponding
addresses in a mask ROM version will always return 1s, and writes to these addresses are disabled.
Rev.3.00 Mar. 26, 2007 Page 442 of 682
REJ09B0353-0300