HD64F3039F18 Datasheet, PDF (316/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
9.1.2 Block Diagram
Figure 9.1 shows a block diagram of the TPC.
ITU compare match signals
Control logic
PADDR
NDERA
TPMR
PBDDR
NDERB
TPCR
TP₁₅
(TP₁₄)*
TP₁₃
TP₁₂
TP₁₁
TP₁₀
TP₉
TP₈
TP₇
TP₆
TP₅
TP₄
TP₃
TP₂
TP₁
TP₀
Pulse output
pins, group 3
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
PBDR
PADR
NDRB
NDRA
Legend:
TPMR: TPC output mode register
TPCR: TPC output control register
NDERB: Next data enable register B
NDERA: Next data enable register A
PBDDR: Port B data direction register
PADDR: Port A data direction register
NDRB: Next data register B
NDRA: Next data register A
PBDR: Port B data register
PADR: Port A data register
Note: * Since this LSI does not have this pin, this signal cannot be output to the outside.
Figure 9.1 TPC Block Diagram
Internal
data bus
Rev.3.00 Mar. 26, 2007 Page 292 of 682
REJ09B0353-0300