HD64F3039F18 Datasheet, PDF (495/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 15 ROM
15.6.3 Error Protection
In error protection, an error is detected when this LSI runaway occurs during flash memory
programming/erasing*¹, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the LSI malfunctions during flash memory programming/erasing, the FLER bit*² is set to 1 in
flash memory status register (FLMSR) and the error protection state is entered. The FLMCR and
EBR settings*³ are retained, but program mode or erase mode is aborted at the point at which the
error occurred. When 1 is set in the FLER bit, transition to the program mode or erase mode
cannot be made even by setting the P and E bits in FLMCR. However, PV and EV bit in FLMCR
setting is enabled, and a transition can be made to verify mode.
Error protection is released only by a reset via the RES pin or a WDT reset, or in the hardware
standby mode.
Figure 15.13 shows the flash memory state transition diagram.
Notes: 1. This is the state in which the P or E bit in FLMCR is set to 1. In this state, NMI input is
disabled. For more information, see section 15.6.4, NMI Input Disable Conditions.
2. For a detailed description of the FLER bits setting conditions, see section 15.3.4, Flash
Memory Status Register (FLMSR).
3. Data can be written to FLMCR and EBR. However, when transition to the software
standby mode was made in the error protection state, the registers are initialized.
Rev.3.00 Mar. 26, 2007 Page 471 of 682
REJ09B0353-0300