HD64F3039F18 Datasheet, PDF (20/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

12.3.4 Register Settings .................................................................................................. 401
12.3.5 Clock.................................................................................................................... 403
12.3.6 Data Transfer Operations..................................................................................... 405
12.4 Usage Note........................................................................................................................ 411
Section 13 A/D Converter................................................................................................. 415
13.1 Overview........................................................................................................................... 415
13.1.1 Features................................................................................................................ 415
13.1.2 Block Diagram..................................................................................................... 416
13.1.3 Input Pins ............................................................................................................. 417
13.1.4 Register Configuration......................................................................................... 418
13.2 Register Descriptions ........................................................................................................ 419
13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 419
13.2.2 A/D Control/Status Register (ADCSR) ............................................................... 420
13.2.3 A/D Control Register (ADCR) ............................................................................ 422
13.3 CPU Interface.................................................................................................................... 423
13.4 Operation .......................................................................................................................... 424
13.4.1 Single Mode (SCAN = 0) .................................................................................... 424
13.4.2 Scan Mode (SCAN = 1)....................................................................................... 426
13.4.3 Input Sampling and A/D Conversion Time ......................................................... 428
13.4.4 External Trigger Input Timing............................................................................. 429
13.5 Interrupts........................................................................................................................... 430
13.6 Usage Notes ...................................................................................................................... 430
Section 14 RAM .................................................................................................................. 435
14.1 Overview........................................................................................................................... 435
14.1.1 Block Diagram..................................................................................................... 436
14.1.2 Register Configuration......................................................................................... 436
14.2 System Control Register (SYSCR) ................................................................................... 437
14.3 Operation .......................................................................................................................... 438
Section 15 ROM .................................................................................................................. 439
15.1 Overview........................................................................................................................... 439
15.2 Overview of Flash Memory .............................................................................................. 440
15.2.1 Features................................................................................................................ 440
15.2.2 Block Diagram..................................................................................................... 441
15.2.3 Pin Configuration................................................................................................. 442
15.2.4 Register Configuration......................................................................................... 442
15.3 Register Descriptions ........................................................................................................ 443
15.3.1 Flash Memory Control Register (FLMCR).......................................................... 443
15.3.2 Erase Block Register (EBR) ................................................................................ 447
Rev.3.00 Mar. 26, 2007 Page xviii of xxii
REJ09B0353-0300