HD64F3039F18 Datasheet, PDF (284/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
TCNT4
T
T–1
H'0000
H'FFFF
TCNT3
Illegal changes
Figure 8.41 Changing a General Register Setting by Buffer Transfer (Caution 2)
 General register settings outside the counting range (H'0000 to GRA3)
Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to
a value outside the counting range. When a buffer register is set to a value outside the
counting range, then later restored to a value within the counting range, the counting
direction (up or down) must be the same both times. See figure 8.42.
GRA3
GR
H'0000
Output pin
Output pin
0% duty cycle
100% duty cycle
BR
GR
Write during down-counting
Write during up-counting
Figure 8.42 Changing a General Register Setting by Buffer Transfer (Example 2)
Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow
before writing to the buffer register.
Rev.3.00 Mar. 26, 2007 Page 260 of 682
REJ09B0353-0300