HD64F3039F18 Datasheet, PDF (306/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, the counter is
cleared according to the input capture signal. The counter is not incremented by the increment
signal. The value before the counter is cleared is transferred to the general register. See figure
8.67.
φ
Input capture signal
Counter clear signal
TCNT input clock
TCNT
N
H'0000
GR
N
Figure 8.67 Contention between Counter Clearing by Input Capture and
Counter Increment
Rev.3.00 Mar. 26, 2007 Page 282 of 682
REJ09B0353-0300