HD64F3039F18 Datasheet, PDF (64/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 2 CPU
Table 2.10 Block Transfer Instruction
Instruction
EEPMOV.B
EEPMOV.W
Size
—
Function
if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until R4L = 0
else next;
if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until R4 = 0
else next;
Transfers a data block according to parameters set in general registers
R4L or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5:
Starting source address
ER6:
Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.4 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Rev.3.00 Mar. 26, 2007 Page 40 of 682
REJ09B0353-0300