HD64F3039F18 Datasheet, PDF (79/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 2 CPU
φ
Address bus
T₁
T₂
Address
AS, RD, WR
D₇ to D₀
High
High impedance
Figure 2.16 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2.17 shows the on-chip supporting module access
timing. Figure 2.18 indicates the pin states.
φ
Internal address bus
Read
access
Internal read signal
Internal data bus
T₁ state
Bus cycle
T₂ state
T₃ state
Address
Read data
Write
access
Internal write signal
Internal data bus
Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
Rev.3.00 Mar. 26, 2007 Page 55 of 682
REJ09B0353-0300