HD64F3039F18 Datasheet, PDF (353/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 10 Watchdog Timer
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 10.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3039 Group chip. This internal reset signal clears OVF to 0, but the
WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
WDT internal
reset
WRST
Figure 10.7 Timing of Setting of WRST Bit and Internal Reset
10.4 Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
Rev.3.00 Mar. 26, 2007 Page 329 of 682
REJ09B0353-0300