HD64F3039F18 Datasheet, PDF (65/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Figure 2.9 shows examples of instruction formats.
Section 2 CPU
Operation field only
op
NOP, RTS, etc.
Operation field and register fields
op
rn
rm
ADD.B Rn, Rm, etc.
Operation field, register fields, and effective address extension
op
rn
rm
EA (disp)
MOV.B @(d:16, Rn), Rm
Operation field, effective address extension, and condition field
op
cc
EA (disp)
Figure 2.9 Instruction Formats
BRA d:8
2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead
of time.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
Rev.3.00 Mar. 26, 2007 Page 41 of 682
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