HD64F3039F18 Datasheet, PDF (325/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
9.2.7 Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP₇ to TP₀) on a bit-by-bit basis.
Bit
Initial value
Read/Write
7
NDER7
0
R/W
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to
the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP₇ to TP₀) on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0
0
1
Description
TPC outputs TP₇ to TP₀ are disabled
(NDR to NDR0 are not transferred to PA to PA )
7
7
0
TPC outputs TP₇ to TP₀ are enabled
(NDR₇ to NDR₀ are transferred to PA₇ to PA₀)
(Initial value)
Rev.3.00 Mar. 26, 2007 Page 301 of 682
REJ09B0353-0300