HD64F3039F18 Datasheet, PDF (293/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.4.9 ITU Output Timing
The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external
trigger, or inverted by bit settings in TOCR.
Timing of Enabling and Disabling of ITU Output by TOER
In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER. An
arbitrary value can be output by appropriate settings of the data register (DR) and data direction
register (DDR) of the corresponding input/output port. Figure 8.54 illustrates the timing of the
enabling and disabling of ITU output by TOER.
T₁
T₂
T₃
φ
Address
TOER address
TOER
ITU output pin
Timer output
I/O port
ITU output
Generic input/output
Figure 8.54 Timing of Disabling of ITU Output by Writing to TOER (Example)
Rev.3.00 Mar. 26, 2007 Page 269 of 682
REJ09B0353-0300