HD64F3039F18 Datasheet, PDF (155/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

6.4 Usage Notes
Section 6 Bus Controller
6.4.1 Register Write Timing
ASTCR and WCER Write Timing
Data written to ASTCR or WCER takes effect starting from the next bus cycle. Figure 6.11 shows
the timing when an instruction fetched from area 2 changes area 2 from three-state access to two-
state access.
T₁
T₂
T₃
T₁
T₂
T₃
T₁
T₂
φ
Address
ASTCR address
3-state access to area 2
2-state access
to area 2
Figure 6.11 ASTCR Write Timing
6.4.2 Precautions on Setting ASTCR and ABWCR*
Use the H8/3039 Group on-chip program to set ASTCR and ABWCR as shown below, so that the
on-chip ROM access cycle for H8/3039 Group can be emulated using the evaluation chip for
support tools.
Modes 5 and 7
ASTCR0 = 0
ABWCR = H'FC
Note: * The ABWCR (bus width control register; lower 16-bit address: H'FFEC) is not built
onto this LSI. For detailed features of the ABWCR, see the H8/3048 Group,
H8/3048F-ZTAT^TM Hardware Manual.
Rev.3.00 Mar. 26, 2007 Page 131 of 682
REJ09B0353-0300