HD64F3039F18 Datasheet, PDF (218/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.1.2 Block Diagrams
ITU Block Diagram (Overall)
Figure 8.1 is a block diagram of the ITU.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TOCXA₄, TOCXB₄
TIOCA₀ to TIOCA₄
TIOCB₀ to TIOCB₄
Clock selector
Control logic
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
TOER
TOCR
TSTR
TSNC
TMDR
TFCR
Module data bus
Legend:
TOER: Timer output master enable register (8 bits)
TOCR: Timer output control register (8 bits)
TSTR: Timer start register (8 bits)
TSNC: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
TFCR: Timer function control register (8 bits)
Figure 8.1 ITU Block Diagram (Overall)
Rev.3.00 Mar. 26, 2007 Page 194 of 682
REJ09B0353-0300