HD64F3039F18 Datasheet, PDF (496/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 15 ROM
P=1 or E=1
Memory read verify mode
RD VF PR ER FLER = 0
P = 0 and E = 0
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Program mode
Reset or standby mode
Erase mode
Reset or hardware standby mode
(hardware protection)
RD VF PR ER FLER = 0
Error occurrence
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RD VF PR ER INIT FLER = 0
Reset or hardware
standby mode
Error protection mode
RD VF PR ER FLER = 1
Software
standby mode
Software standby
mode release
Error protection mode
(software standby mode)
RD VF PR ER INIT FLER = 1
Legend:
RD: Memory read enable
VF: Verify-read enable
PR: Programming enable
ER: Erasing enable
RD: Memory read disabled
VF: Verify-read disabled
PR: Programming disabled
ER: Erasing disabled
INIT: Registers (FLMCR, EBR) initialize state
Figure 15.13 Flash Memory State Transitions
(When High Level Apply to FWE Pin in Modes 5 and 7 (On-Chip ROM Enabled))
The error protection function is disabled for errors other than the FLER bit set conditions. If
considerable time elapses up to transit to this protection state, the flash memory may already be
damaged. As a result, this function cannot completely protect the flash memory against damage.
Therefore, to prevent such erroneous operation, operation must be carried out correctly in
according with the program/erase algorithms in the state that flash write enable (FWE) is set. In
addition, the operation must be always carried out correctly by supervising microcomputer errors
inside and outside the chip with the watchdog timer, etc. At transition to this protection mode, the
flash memory may be erroneously programmed or erased, or its abort may result in incomplete
Rev.3.00 Mar. 26, 2007 Page 472 of 682
REJ09B0353-0300