HD64F3039F18 Datasheet, PDF (302/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Contention between TCNT Byte Write and Increment
If an increment pulse occurs in the T₂ or T₃ state of a TCNT byte write cycle, writing takes priority
and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See
figure 8.63, which shows an increment pulse occurring in the T₂ state of a byte write to TCNTH.
TCNTH byte write cycle
T₁
T₂
T₃
φ
Address
TCNTH address
Internal write signal
TCNT input clock
TCNTH
TCNTL
N
M
TCNT write data
X
X+1
X
Figure 8.63 Contention between TCNT Byte Write and Increment
Rev.3.00 Mar. 26, 2007 Page 278 of 682
REJ09B0353-0300