HD64F3039F18 Datasheet, PDF (604/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Appendix A Instruction Set
A.3 Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A.3 indicates the number of states required per cycle
according to the bus size. Table A.4 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × S_I + J × S_J + K × S_K + L × S_L + M × S_M + N × S_N
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFC7:8
From table A.3, S_I = 4 and S_L = 3
From table A.4, I = L = 2 and J = K = M = N = 0
Number of states = 2 × 4 + 2 × 3 = 14
JSR @@30
From table A.3, S_I = S_J = S_K = 4
From table A.4, I = J = K = 2 and L = M = N = 0
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
Rev.3.00 Mar. 26, 2007 Page 580 of 682
REJ09B0353-0300