HD64F3039F18 Datasheet, PDF (238/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.2.5 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit
7
—
Initial value
1
Read/Write
—
6
5
4
3
2
1
0
—
EXB4 EXA4 EB3
EB4
EA4
EA3
1
1
1
1
1
1
1
—
R/W
R/W R/W
R/W
R/W R/W
Reserved bits
Master enable TOCXA₄, TOCXB₄
These bits enable or disable output
settings for pins TOCXA₄ and TOCXB₄
Master enable TIOCA₃, TIOCB₃ , TIOCA₄, TIOCB₄
These bits enable or disable output settings for pins
TIOCA₃, TIOCB₃ , TIOCA₄, and TIOCB₄
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
Bit 5—Master Enable TOCXB₄ (EXB4): Enables or disables ITU output at pin TOCXB₄.
Bit 5
EXB4
0
1
Description
TOCXB output is disabled regardless of TFCR settings (TOCXB operates as a generic
4
4
input/output pin). If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in
channel 1.
TOCXB₄ is enabled for output according to TFCR settings
(Initial value)
Bit 4—Master Enable TOCXA₄ (EXA4): Enables or disables ITU output at pin TOCXA₄.
Bit 4
EXA4
0
1
Description
TOCXA output is disabled regardless of TFCR settings (TOCXA operates as a generic
4
4
input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
TOCXA₄ is enabled for output according to TFCR settings
(Initial value)
Rev.3.00 Mar. 26, 2007 Page 214 of 682
REJ09B0353-0300