HD64F3039F18 Datasheet, PDF (329/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP₇ to TP₄).
Bit 3
G1CMS1
0
1
Bit2
G1CMS0
0
1
0
1
Description
TPC output group 1 (TP₇ to TP₄) is triggered by compare match in
ITU channel 0
TPC output group 1 (TP₇ to TP₄) is triggered by compare match in
ITU channel 1
TPC output group 1 (TP to TP ) is triggered by compare match in
7
4
ITU channel 2
TPC output group 1 (TP₇ to TP₄) is triggered by compare match in
ITU channel 3
(Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP₃ to TP₀).
Bit1
G0CMS1
0
1
Bit0
G0CMS0
0
1
0
1
Description
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in
ITU channel 0
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in
ITU channel 1
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in
ITU channel 2
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in
ITU channel 3
(Initial value)
Rev.3.00 Mar. 26, 2007 Page 305 of 682
REJ09B0353-0300