HD64F3039F18 Datasheet, PDF (308/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Contention between Buffer Register Write and Input Capture
If a buffer register is used for input capture buffering and an input capture signal occurs in the T₃
state of a write cycle, input capture takes priority and the write to the buffer register is not
performed. See figure 8.69.
Buffer register write cycle
T₁
T₂
T₃
φ
Address
BR address
Internal write signal
Input capture signal
GR
N
X
TCNT value
BR
M
N
Figure 8.69 Contention between Buffer Register Write and Input Capture
Rev.3.00 Mar. 26, 2007 Page 284 of 682
REJ09B0353-0300