HD64F3039F18 Datasheet, PDF (78/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 2 CPU
2.9 Basic Operational Timing
2.9.1 Overview
The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the
system clock to the next rise is referred to as a "state." A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin
states.
Bus cycle
T₁ state
T₂ state
φ
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.15 On-Chip Memory Access Cycle
Rev.3.00 Mar. 26, 2007 Page 54 of 682
REJ09B0353-0300