HD64F3039F18 Datasheet, PDF (392/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 11 Serial Communication Interface
In receiving, the SCI operates as follows.
• The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes
internally and starts receiving.
• Receive data is stored in RSR in order from LSB to MSB.
• The parity bit and stop bit are received.
After receiving data, the SCI makes the following checks:
 Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
 Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop
bit is checked.
 Status check: The RDRF flag must be 0 so that receive data can be transferred from
RSR into RDR.
If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one
of the checks fails (receive error)*, the SCI operates as indicated in table 11.11.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
is not set to 1. Be sure to clear the error flags.
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Table 11.11 Receive Error Conditions
Receive Error
Overrun error
Framing error
Parity error
Abbreviation
ORER
FER
PER
Condition
Data Transfer
Receiving of next data ends Receive data not transferred
while RDRF flag is still set to 1 from RSR to RDR
in SSR
Stop bit is 0
Receive data transferred
from RSR to RDR
Parity of receive data differs Receive data transferred
from even/odd parity setting in from RSR to RDR
SMR
Rev.3.00 Mar. 26, 2007 Page 368 of 682
REJ09B0353-0300