HD64F3039F18 Datasheet, PDF (300/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.6 Usage Notes
This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear
If a counter clear signal occurs in the T₃ state of a TCNT write cycle, clearing of the counter takes
priority and the write is not performed. See figure 8.61.
TCNT write cycle
T₁
T₂
T₃
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'0000
Figure 8.61 Contention between TCNT Write and Clear
Rev.3.00 Mar. 26, 2007 Page 276 of 682
REJ09B0353-0300