HD64F3039F18 Datasheet, PDF (294/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Timing of Disabling of ITU Output by External Trigger
If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary
PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are
cleared to 0 in TOER, disabling ITU output. Figure 8.55 shows the timing.
φ
TIOCA₁ pin
Input capture
signal
TOER
N
H'C0
N
H'C0
ITU output
pins
ITU output
ITU output
Legend:
N: Arbitrary setting (H'C1 to H'FF)
I/O port
Generic
input/output
ITU output
ITU output
I/O port
Generic
input/output
Figure 8.55 Timing of Disabling of ITU Output by External Trigger (Example)
Rev.3.00 Mar. 26, 2007 Page 270 of 682
REJ09B0353-0300