HD64F3039F18 Datasheet, PDF (413/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 11 Serial Communication Interface
Restrictions when Switching from SCK Pin to Port Function in Synchronous SCI
1. Problem in Operation
After setting DDR and DR to 1 and using synchronous SCI clock output, when the SCK pin is
switched to the port function at the end of transmission, a low-level signal is output for one
half-cycle before the port output state is established.
When switching to the port function by making the following settings while DDR = 1, DR = 1,
C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, low-level output occurs for one half-cycle.
(1) End of serial data transmission
(2) TE bit = 0
(3) C/A bit = 0 ... switchover to port output
(4) Occurrence of low-level output (see figure 11.23)
Half-cycle low-level output occurs
SCK/port
Data
TE
C/A
Bit 6
(1) End of transmission
Bit 7
(2) TE = 0
(4) Low-level output
(3) C/A = 0
CKE1
CKE0
Figure 11.23 Operation when Switching from SCK Pin Function to Port Pin Function
Rev.3.00 Mar. 26, 2007 Page 389 of 682
REJ09B0353-0300