HD64F3039F18 Datasheet, PDF (342/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 10 Watchdog Timer
10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the WDT.
Overflow
Interrupt signal
Interrupt
(interval timer) ^control
TCNT
TCSR
RSTCSR
Reset
(internal, external)
Reset control
Clock
Clock
selector
Legend:
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
Figure 10.1 WDT Block Diagram
Read/
write
control
Internal
data bus
Internal clock sources
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
10.1.3 Pin Configuration
Table 10.1 describes the WDT output pin.*
Note: * Shows the mask ROM version pin. The F-ZTAT does not have any pins used by the
WDT. For F-ZTAT version, see section 15.9, Notes on Flash Memory
Programming/Erasing.
Table 10.1 WDT Pin
Name
Abbreviation I/O
Function
Reset output RESO
Output* External output of the watchdog timer reset signal
Note: * Open-drain output. Externally pull-up to Vcc whether or not the reset output is used
Rev.3.00 Mar. 26, 2007 Page 318 of 682
REJ09B0353-0300