HD64F3039F18 Datasheet, PDF (303/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Write and Compare Match
If a compare match occurs in the T₃ state of a general register write cycle, writing takes priority
and the compare match signal is inhibited. See figure 8.64.
General register write cycle
T₁
T₂
T₃
φ
Address
GR address
Internal write signal
TCNT
N
N+1
GR
Compare match signal
N
M
General register write data
Inhibited
Figure 8.64 Contention between General Register Write and Compare Match
Rev.3.00 Mar. 26, 2007 Page 279 of 682
REJ09B0353-0300