HD64F3039F18 Datasheet, PDF (352/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 10 Watchdog Timer
10.3.3 Timing of Setting of Overflow Flag (OVF)
Figure 10.6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when
TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an
interval timer interrupt is generated in interval timer operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 10.6 Timing of Setting of OVF
Rev.3.00 Mar. 26, 2007 Page 328 of 682
REJ09B0353-0300