HD64F3039F18 Datasheet, PDF (332/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP₃ to TP₀).
Bit 0
G0NOV
0
1
Description
Normal TPC output in group 0 (output values change at compare match A in the
selected ITU channel)
(Initial value)
Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare
match A and B in the selected ITU channel)
9.3 Operation
9.3.1 Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 9.2 illustrates the TPC output operation. Table 9.3 summarizes the TPC operating
conditions.
DDR
Q
NDER
Q
Output trigger signal
TPC output pin
C
Q DR D
Q NDR D
Internal
data bus
Figure 9.2 TPC Output Operation
Rev.3.00 Mar. 26, 2007 Page 308 of 682
REJ09B0353-0300