HD64F3039F18 Datasheet, PDF (339/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

9.4 Usage Notes
Section 9 Programmable Timing Pattern Controller
9.4.1 Operation of TPC Output Pins
TP₀ to TP₁₅* are multiplexed with ITU pin functions. When ITU output is enabled, the
corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits
takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
Note: * Since this LSI does not have a TP₁₄ pin, the TP₁₄ signal cannot be output to the outside.
9.4.2 Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 9.9 illustrates the non-overlapping TPC output operation.
DDR
Q
NDER
Q
Compare match A
Compare match B
TPC output pin
C
Q DR D
Q NDR D
Figure 9.9 Non-Overlapping TPC Output
Rev.3.00 Mar. 26, 2007 Page 315 of 682
REJ09B0353-0300